1. Field of the Invention
At least one example embodiment relates to a method of fabricating a semiconductor device and/or a computing system for implementing the method.
2. Description of the Related Art
As semiconductor devices become more highly integrated, a pattern size of the semiconductor device is being rapidly reduced. Accordingly, a process margin for forming fine patterns of a semiconductor device has been reduced. For example, while fabricating a semiconductor device, various patterns including metal wirings are formed using, for example, a photolithography process.
The photolithography process generally consists of a coating process for coating photoresist on an etch target layer, an exposure process for irradiating light to a predetermined (or alternatively, desired portion) of the coated photoresist, and a development process for removing the exposed portion of the photoresist. A desired pattern is formed by etching an etch target layer using a photoresist pattern.
As the integration of semiconductor devices advances, the importance of a fine pattern forming technology also increases. However, because a critical dimension of photoresist that can be implemented by photolithography equipment is limited to a certain range, it becomes more and more difficult to form fine patterns. To address this issue, double patterning lithography has been suggested as a technology to form fine patterns having a line width within the certain range or less.
However, because some patterns are still difficult to pattern even using double patterning lithography, research is being actively conducted on a method of forming such challenging patterns in a reliable manner.